Additive electroplating processes on targeted areas of the surface of a semiconductor device are established bumping technologies in the semiconductor industry. Two primary components for electroplating targeted areas on the surface of a semiconductor device include a deposited conductive metal seed layer (which can be comprised of one, two or more stacked layers of deposited metal) that provides an electrically continuous current pathway to the targeted areas of the device, and a masking-type resist material on top of the metal seed layer that defines the areas targeted for plating by covering the areas where additive plating is not desired.
The use of additive electroplating bumping technologies has oftentimes been frustrated by the absence of plating occurring in all targeted locations or with locations having severely uneven plating. Subsequent analysis has routinely determined that the deposited metal seed layer had been discontinuous due to the topography of wafer features. The most predominant type of topographical issue causing discontinuity or break in the metal seed layer is an adverse sidewall profile of a dielectric layer(s) or a slightly lifted dielectric layer(s) at the dielectric edges beneath the deposited seed layer.
Semiconductor fabricators have desired to ensure that their processes create dielectric edges around each die that have the appropriate sidewall angles and to keep the dielectric layer from lifting up at the edges to ensure subsequently-deposited metal seed layers have a continuous conductive pathway over the surface of the wafer. Some fabricators have attempted to solve this problem by creating one continuous blanket layer of dielectric covering the wafer, requiring them to dice through this layer (but most fabricators choose not to do this due to the complications it causes). It has been widely known in the industry for more than 25 years that keeping saw streets clear of dielectric is an important practice to avoid chipping of the dielectric and resultant poor dicing quality.